The Debug Task Group's goal is the ratification of a specification for how to enable low-level hardware debugging on RISC-V implementations. In this section of the RISC-V Foundation Workspace you will find meeting minutes and slides, updated on a regular basis.
Access to this area is restricted to members of the Debug Task Group.
Fast Interrupts TG
The Fast Interrupts task group is focused on developing a low-latency, vectored, priority-based, preemptive interrupt scheme for interrupts directed to a single hart, compatible with the existing RISC-V standards.
This group will produce a Formal Specification for the RISC-V ISA. This is a specification of the ISA in a formal language, for precision, unambiguity, consistency and completeness.
It should be readable and understandable as a canonical reference by practising CPU architects and compiler writers. It should executable and machine-manipulable for use in formal tools for establishing correctness and transformations in both compilers and CPU designs.
[ This work is closely related to and complementary to the work of the Memory Model Task Group ]
The RISC-V Marketing Committee is responsible for shaping RISC-V in the market place. Our goals are to increase awareness among developers, software & hardware engineers, architects, CTOs and others who influence technical decisions. We aim to accurately deliver the compelling story of RISC-V such that it becomes an admired brand and by extension this will create a halo over all RISC-V members who use it.
The memory model task group charter is to define the memory consistency model for the RISC-V architecture, to produce relevant documentation and supplementary material (such as formal mathematical specifications and compliance test cases), and to work with the other task groups to ensure their own specifications remain compatible with the memory mode
Opcode Space Management
The OpCode Space Management Task Group is a standing group with the
task of allocating reserved opcode space for new proposed standard
extensions. The group works with task groups developing new standard
extensions to avoid conflicts with other current and planned future
The Privileged Architecture Task Group's charter is to define and facilitate the ratification of a Privileged Architecture Specification suitable for embedded systems and Unix-like operating systems.
SW Tool Chain
Welcome to the Software Task Group. The goal of this task group is to coordinate efforts to build the RISC-V software ecosystem and to standardize RISC-V software interfaces.
The Technical Committee is responsible for maintaining the RISC-V ISA. This includes maintenance of specifications, errata, future enhancements, and any technical activities necessary to promote or enable the technology. The charter of the committee is to promote a coherent, usable specification and make available either directly or indirectly a set of collateral materials to promote the use of the RISC-V ISA.
RISC-V ISA Specification Ratification Process
Any proposed release or revision of RISC-V ISA or related specifications shall follow the governance process detailed in the RISC-V Foundation Bylaws section 5.5 (shown below),
5.5 COMMITTEE REPORTS
Committee Reports shall be made publicly available online via the RISC-V website (www.riscv.org) for external comments and discussion for at least forty-five (45) days before the Board votes on the Committee Reports. The Committee Reports forwarded to the Board shall include a document with the Committee's response to issues raised by Committee members who voted against such Committee Report and by any dissenting public comments.
The V Extension Task Group is tasked with developing the
specification for the RISC-V base V vector extension, including
written documentation, executable model, and compliance suite. The
group is also responsible for outlining how future vector extensions
can build on this baseline.